The present invention relates to an ATM (Asynchronous Transfer Mode) cell multiplexing apparatus and, more particularly, to an ATM cell multiplexing apparatus which multiplexes a plurality of cell streams for transferring cells each having a predetermined length in an ATM communication system.
Such an ATM cell multiplexing apparatus is disclosed in, e.g., Japanese Patent Laid-Open No. 4-40718. The cell multiplexing method of this apparatus is as follows. As shown in FIG. 11, data in input signals 11-1, 11-2, . . . , 11-n each having a cell stream are written in FIFO (First-In First-Out) memories 12-1, 12-2, . . . , 12-n serving as cell generators, respectively, in units of bytes. The data are accumulated in the FIFO memories 12-1, 12-2, . . . , 12-n to constitute cells, respectively. When read access in units of cells is enabled, cell send request signals 13-1, 13-2, . . . , 13-n are output from the FIFO memories 12-1, 12-2, . . . , 12-n to a cell send arbiter 15.
The cell send arbiter 15 processes the cell send request (RDY) signals 13-1, 13-2, . . . , 13-n and issues a cell send permission signal to one FIFO memory (12-n). Accumulated cell information is read out from the FIFO memory applied with the right therefor.
With this operation, cell data from the FIFO memories 12-1, 12-2, . . . , 12-n are sent as cell send permission (OE) signals 16A to 16D. These signals are byte-multiplexed by a byte multiplexing parallel/serial converter 17 so that a serial signal 18 is sent. A timing signal generator 19 generates a transfer clock 20 and cell send start timing signals A to D.
The cell send arbiter 15 will be described below with reference to FIGS. 12 and 13. FIG. 12 shows an example of a circuit 60 constituting the cell send arbiter shown in FIG. 11. FIG. 13 shows an example of a selector shown in FIG. 12. Assume that a memory 74 of a selector 60-3 (n=3) is at high level, and an ENo signal 62-3 is at high level.
In this state, when the RDY signals 13-1, 13-2, . . . , 13-n are not input to all selectors 60-1, 60-2, . . . , 60-n, AND circuits 71 and OR circuits 72 of all the selectors except for the selector 60-3 output signals at high level, and data send right output (ENo) signals are also at high level. This state will be referred to as a cell send right transfer state.
At this time, when the RDY signal 13-8 at high level is input to one of the selectors including the selector 60-3 in the cell send right transfer state, e.g., the selector 60-8 (n=8), the AND circuit 71 and OR circuit 72 of the selector 60-8 output signals at low level, and an ENo signal 62-8 goes low. This state will be referred to as a cell send right acquisition state.
All the selectors on the downstream side of the selector 60-8 in the cell send right acquisition state are set in a waiting state. Assume that, when the selector 60-8 is in the cell send right acquisition state, one of the selectors in the cell send right transfer state between the selector 60-3 and the selector 60-8 in the cell send right issue state, e.g., the selector 60-5 (n=5) receives the RDY signal 13-5 at high level. At this time, the selector 60-5 is immediately set in the cell send right acquisition state, and all the selectors on the downstream side of the selector 60-5 are set in the waiting state.
Therefore, the selector 60-8 loses the cell send right. More specifically, selectors closer to the selector 60-3 in the cell send right issue state are applied with a higher priority.
The first problem is that, in the prior art, as shown in FIG. 11, as the number of input ports 11-n (n is an integer) increases, the number of circuits 60 in the cell send arbiter 15 for cell send arbitration increases. The reason for this is that since read control for the FIFO memories 12-n to each input port 11-n is individually performed by independent circuits, another identical control circuit is necessary for a new input port.
The second problem is as follows. The above-described cell send arbiter 15 has a daisy chain configuration (in which circuit networks are connected in series with each other to form a chain-like configuration), as shown in FIG. 12. For this reason, a data send right is always imparted to only upper input ports (ports whose n is small). If cells frequently arrive at the upper input ports, and simultaneously, at lower input ports, the FIFO memories overflow with the cells unless the capacities of the FIFO memories of these input ports are largely increased. This is because the cell send arbiter has a series-connected chain-like configuration.